1. Field of the Invention
The present invention relates to a semiconductor gate circuit for effecting a predetermined processing on an applied signal for outputting, and in particular to a buffer circuit or a delay circuit in which rising and falling times of an output signal or a delay time thereof has a reduced dependency on a power supply voltage.
2. Description of the Background Art
Portable information equipments have recently been widely used. Many portable information equipments use batteries as their power sources. Therefore, elements used in such a portable information equipment are required to operate fast for a long time with a small number of batteries. In a semiconductor device, however, if the power supply voltage is simply lowered for reducing the power consumption without changing a conventional circuit structure, a current driving capability of a MOS transistor (insulated gate field-effect transistor) abruptly lowers, and therefore an operation speed of the element significantly lowers. This results in significant increase in an access time, if the semiconductor device is a memory. In order to suppress lowering of the current driving capability, it is necessary to reduce an absolute value of a threshold voltage of the MOS transistor in accordance with lowering of the power supply voltage so that the operation speed of the MOS transistor may not lower even with a low power supply voltage. In the case of a low power consumption SRAM (Static Random Access Memory), however, there is a strict restriction on a current during standby (that a standby current must be about 1 .mu.A), so that even a leak current alone which flows through an off state MOS transistor exceeds a specification value if measures other than reduction in absolute value of the threshold voltage are not employed. This is due to a subthreshold current of the MOS transistor. The subthreshold current is a current which flows when Et gate to source voltage lowers to or below the threshold voltage (in the case of the n-channel MOS transistor).
FIG. 43 shows a relationship between a gate-source voltage Vgs and a drain current Ids in a subthreshold region of an n-channel MOS transistor. In FIG. 43, the abscissa gives gate-source voltage Vgs, and the ordinate gives, on a logarithmic scale, the drain current Ids. The subthreshold region is a region in which curves S1 and S2 extend straight. The drain current exponentially lowers in accordance with a difference between the gate voltage and the threshold voltage. Threshold voltage Vth of the MOS transistor is defined as a gate-source voltage which causes flow of a predetermined current Ith in a MOS transistor having a predetermined gate width. Therefore, the MOS transistor having drain current characteristics represented by curve Si in FIG. 43 has the threshold voltage of Vtha. If the threshold voltage of MOS transistor is lowered from Vtha to Vthb, characteristics represented by curve S2 is obtained. When the MOS transistor is off, the gate-source voltage Vgs is 0V, and a current I0 flows in the MOS transistor having threshold voltage Vtha, while a current I1 flows in the MOS transistor having threshold voltage Vthb. In the n-channel MOS transistor, therefore, the leak current (subthreshold current) in the off state increases with decrease in threshold voltage. For example, when threshold voltage Vth lowers by 0.3 V, the leak current of the MOS transistor increases 1000 times, resulting in flow of a leak current larger than the standby leak current prescribed in the specification.
In an inverter buffer using MOS transistors, if a only standard MOS transistors, i.e., MOS transistors having threshold voltages of ordinary absolute values are employed, the current consumption during standby can be reduced, but rising and falling times of an output signal increase during an operation with a low power supply voltage due to lowering of the current driving capability of the MOS transistors during the operation with the low power supply voltage. This impairs the input/output characteristics. Particularly in a delay circuit formed of a plurality of cascaded inverter buffers, a dependency of a delay time on the power supply voltage increases during the operation with the low power supply voltage, so that it is impossible to change internal signals at desired timings. For use with a low power supply voltage, therefore, a semiconductor gate circuit such as an inverter buffer or a delay circuit is required to satisfy the following two conditions.
1. A drive current value is determined by a low-Vth transistor, i.e., a MOS transistor of which threshold voltage is reduced in absolute value in accordance with lowering of the power supply voltage and of which current driving capability does not significantly lower even with a low power supply voltage.
2. During standby, a leak current hardly flows. Thus, a standard MOS transistor is necessarily arranged at every current path, and this MOS transistor is held in the off state during standby.
FIG. 44 shows an example of a structure of a conventional delay circuit which has been devised to satisfy the foregoing two conditions. In FIG. 44, the delay circuit includes four cascaded inverters IV1, IV2, IV3 and IV4. Each of inverters IV1-IV4 operates receiving as operation power supply voltages a power supply voltage on a power supply node 1 and a ground voltage on a ground node 2. Each of inverters IV1-IV4 includes a p-channel MOS transistor PQL and an n-channel MOS transistor NQL which are connected in series between power supply node 1 and a common node 3 and each receive on its gate an input signal IN or an output signal of the inverter at the immediately preceding stage. MOS transistors PQL and NQL have threshold voltages of small absolute values, respectively.
The delay circuit includes an n-channel MOS transistor NQS, which is selectively turned on in response to control signal .phi.ACT, and thereby electrically connects common node 3 to ground node 2. This MOS transistor NQS is a standard MOS transistor having threshold voltage larger in absolute value than threshold voltages of MOS transistors PQL and NQL. Control signal .phi.ACT specifies a standby cycle and an active cycle in a semiconductor device using this delay circuit. An operation of the delay circuit shown in FIG. 44 will be described below with reference to a signal waveform diagram shown in FIG. 45. During standby, control signal .phi.ACT is at the ground voltage level or L-level, and MOS transistor NQS is off. Thereby, common node 3 is electrically isolated from ground node 2.
MOS transistor NQS has a high threshold voltage, and therefore hardly causes a leak current flowing from common node 3 to ground node 2. In this standby cycle, input signal IN maintains a certain logical level. FIG. 45 shows a signal waveform in the case that input signal IN is fixed to H-level. When input signal IN is at H-level, p- and n-channel MOS transistors PQL and NQL in inverter IV1 are off and on, respectively. In this state, a leak current flows from power supply node 1 to common node 3 through p- and n-channel MOS transistors PQL and NQL. However, MOS transistor NQS is off, so that the leak current flowing into common node 3 does not flow to ground node 2.
In this standby cycle, output signal OUT is held at H-level because the potential on common node 3 rises by the leak current. When input signal IN is at L-level, MOS transistors PQL and NQL in inverter IV1 are on and off, respectively. However, output signal OUT is held at H-level because the leak current likewise flows.
In the active cycle, input signal IN changes in accordance with an operations of another circuit or an externally applied signal. In this active cycle, control signal .phi.ACT is set to the power supply voltage level, i.e., H-level, and MOS transistor NQS is on, so that common node 3 is electrically connected to ground node 2, and common node 3 attains the ground voltage level. In accordance with change of input signal IN from H-level to L-level, output signal OUT falls from H-level to L-level after elapsing of a delay time TD determined by inverters IV1-IV4. When input signal IN rises from L-level to H-level, output signal OUT rises from L-level to H-level after elapsing of a delay time TD'.
When the delay circuit shown in FIG. 44 is used, the operation is performed as follows. While this delay circuit is in a standby state, common node 3 is electrically isolated from ground node 2, so that there is no current path from power supply node 1 to ground node 2. Therefore, leak current IL during standby can be sufficiently suppressed even if low-Vth MOS transistors are used in the inverter circuits. In the active cycle, since common node 3 is set to the ground voltage level, low-Vth MOS transistors PQL and NQL in each of inverters IV1-IV4 are on and off complementarily, so that, even with the low power supply voltage, the output node can be driven with a current driving capability of a magnitude similar to that under a normal power supply voltage, and output signal OUT can be changed in accordance with input signal IN at high speed.
FIG. 46 schematically shows an arrangement of delay circuits in a conventional semiconductor device. In FIG. 46, a semiconductor device SD includes delay circuits DL1, DL2 and DL3 arranged dispersedly. Delay circuits DL1, DL2 and DL3 delay signals .phi.1, .phi.2 and .phi.3 for outputting the same, respectively. Each of delay circuits DL1-DL3 has the same structure as that shown in FIG. 44. However, delay circuits DL1-DL3 may have different delay times, respectively. Delay circuits DL1-DL3 are dispersed to occupy optimum positions in the device in accordance with contents of processing, i.e., signals .phi.1-.phi.3 applied thereto, respectively.
Control signal generating circuit CG generating control signal .phi.ACT must apply control signal .phi.ACT to each of delay circuits DL1-DL3. Therefore, a signal line SGL arranged between control signal generating circuit CG and delay circuits DL1-DL3 extends over a long distance in semiconductor device SD, so that signal line SGL has a large interconnection resistance and a large parasitic capacitance. Therefore, control signal .phi.ACT changes slowly, and delay circuits DL1-DL3 cannot be driven fast, so that response of delay circuits DL1-DL3 is slowed down during changes from the standby cycle to the active cycle and vice versa, which reduces an effect of reducing a current consumption. It is necessary to delay the operation start timings of delay circuits DL1-DL3 in accordance with a delay of control signal .phi.ACT, so that a fast operation cannot be achieved.
Control signal generating circuit CG must rapidly drive the gates of power-cut MOS transistors, i.e., MOS transistors for cutting off the power included in delay circuits DL1-DL3 as well as signal line SGL. This results in a problem that fast driving of the large load requires a large current consumption.
The above problem arises in not only the delay circuits but also a buffer circuit for buffering an applied signal. This is because an inverter buffer is achieved if only inverter IV1 at the initial stage in the delay circuit shown in FIG. 44 is employed.